Content Details

The new protocol analyzer and exerciser from Keysight Technologies expand the product portfolio of PCI Express 6.0 architecture solutions, providing support for advanced PCI Express 6.0 protocol and Compute Express Link verification.

 

It offers high-speed analysis up to 64 GT/s (PAM4), significantly reducing risks, costs, and time associated with the design and validation of silicon chips, end devices, root ports, and prototypes utilizing PCI Express 6.0 technology.

 

Featuring a sleek design, the tool eliminates the need for cable connections during protocol analysis, accelerating test execution and shortening time-to-market for products.

June 28, 2023 – Keysight Technologies, Inc. recently announced the launch of a new PCI Express (PCIe) 6.0 protocol validation tool. 

 

These protocol analyzers and exercisers, which do not require cable connections, provide convenient assistance to semiconductor, computer, and peripheral device manufacturers for performing comprehensive validation of silicon chips, root complexes, and terminal systems in real-time development environments.

 

The PCIe 6.0 specification is a new high-speed serial interface standard released by PCI-SIG to meet the increasing data flow and bandwidth requirements in data centers. This standard offers support for speeds up to 64 GT/s for new designs targeting servers, end devices, switches, storage devices, and computing engines.

 

To ensure interoperability with other PCIe 6.0 compliant designs, device and component manufacturers need protocol testing solutions to validate their PCIe 6.0 technology designs.

 

Keysight Technologies' new PCIe 6.0 protocol analyzer and PCIe 6.0 protocol exerciser effectively meet the aforementioned requirements of design engineers. These cable-free solutions offer various functional tests, helping customers test PCIe 6.0 technology designs more quickly and reliably.

 

The new Keysight Technologies PCIe 6.0 architecture solutions can:

  • Analyze the data link layer/transport layer of PCIe 6.0 technology designs.

 

  • Support all speeds of PCIe technology (2.5 GT/s, 5.0 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, and 64 GT/s [PAM4]) and 1 to 16 channel widths.

 

  • Easily simulate root complexes and end devices when verifying PCIe and Compute Express Link (CXL) technology designs.

 

  • Provide debugging support through visualization and analysis tools for PCIe 6.0 technology and CXL 1.1/2.0 protocols.

 

  • Offer cable-free protocol analysis with a sleek card-edge mechanical (CEM) form factor.

 

  • Provide a complete PCIe 6.0 compliance testing solution applicable throughout the design cycle.

 

Jim Pappas, Technical Program Director at Intel, stated, "I/O technologies based on PCI Express 6.0 have the potential to deliver breakthrough performance in high-performance I/O interfaces. This technology also enables more innovations such as Compute Express Link for accelerator interconnect and Universal Chiplet Interconnect Express for on-chip communication.

 

Several companies, including Keysight Technologies, can now provide protocol analyzers and exercisers for PCIe 6.0 testing, which is crucial for accelerating the development, deployment, and adoption of high-performance I/O technologies on future Intel platforms and across the industry."

 

Al Yanes, President of PCI-SIG, said, "PCI-SIG is delighted to see our member companies, such as Keysight Technologies, beginning to offer PCIe 6.0 technology testing tools to other members.

 

We sincerely appreciate Keysight Technologies' continuous efforts in supporting PCIe technology and their collaboration with other test vendors in dedicating time, effort, and investment to develop new tools that empower our PCI-SIG members to drive the ongoing development of the PCI Express specification."

 

Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight Technologies, stated, "In advancing the development of artificial intelligence applications, it is critical to validate physical and protocol layer devices, including network interface cards, graphics processing units, and accelerators.

 

With the revolutionary PCIe 6.0 protocol analyzer and exerciser, Keysight Technologies further enhances its high-speed I/O and Ethernet physical and protocol layer testing solutions, better supporting the industry in end-to-end design testing."

From June 13 to 14, 2023, Keysight Technologies showcased its new PCIe 6.0 standard protocol solution at the PCI-SIG Developers Conference in Santa Clara, Texas.

Share：

Previous：

The E-Class Formula team has been fined €25,000 for secretly installing an RFID scanner.

Next：

Osram, with its continuous innovation in Hyper Red technology, continues to lead the development of the plant lighting field.

FAQ

  • What is the role of EDA tools in IC design?

    Electronic Design Automation (EDA) tools play a vital role in IC design. These software tools help designers automate and optimize the design process. They assist with tasks such as schematic capture, simulation, synthesis, layout, and verification, improving design productivity and enabling faster time-to-market.

  • What are the major challenges in IC design?

    IC design faces various challenges, including increasing circuit complexity, power consumption, and shrinking transistor sizes. Other challenges include maintaining signal integrity, ensuring manufacturability, and dealing with the growing complexity of design rules and process technologies.

  • What is RTL design in IC design?

    RTL (Register Transfer Level) design is a step in IC design where the behavior and functionality of the circuit are described at the register transfer level. It involves defining the flow of data between registers and the operations performed on that data, without specifying the physical implementation.