CDCVF2509APWR
Clock Generator 20MHz to 175MHz-IN 175MHz-OUT 24-Pin TSSOP T/RCDCVF2509APWR
Clock Generator 20MHz to 175MHz-IN 175MHz-OUT 24-Pin TSSOP T/R
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Manufacturer Part # : CDCVF2509APWR
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Package/Case: TSSOP
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Part Status : ACTIVE
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Brand: Texas Instruments
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Product Categories : Clock buffers
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RoHS:
Quality Assurance
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We have successfully obtained various certification standards and have established our own professional testing laboratory. This ensures that every product we supply to our customers meets the highest quality standards. We adhere to strict testing protocols to maintain the consistency and accuracy of our products. To ensure that our products are original and genuine, we also collaborate with reputable third-party testing facilities to conduct rigorous quality testing. Our commitment to quality extends to meeting industry, legal, regulatory, and ISO 9001:2015 requirements.
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Service & Packaging
Service & Packaging
About After Sales Service
All Parts Extended Quality Guarantee
Initiate the application within 90 days from the shipment date.
Confirm the return or exchange with our staff.
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Regarding packaging, our products are carefully packed in anti-static bags to provide ESD anti-static protection. The outer packaging is durable with secure closure. We support various packaging methods such as Tape and Reel, Cut Tape, Tube, or Tray.
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CDCVF2509APWR DataSheet
Pricing (USD)
Quantity | Unit Price | Ext. Price |
---|---|---|
1 | $9.805 | $9.80 |
200 | $3.795 | $759.00 |
500 | $3.661 | $1,830.50 |
1000 | $3.596 | $3,596.00 |
These prices are subiect to market fluctuations and quote submission is required.
Details
The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device automatically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state.
Unlike many products containing PLLs, the CDCVF2509A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
For application information, see application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (SCAA039).
The CDCVF2509A is characterized for operation from 0°C to 85°C.
Because it is based on PLL circuitry, the CDCVF2509A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.
Key Features
- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Spread Spectrum Clock Compatible
- Operating Frequency 20 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to
166 MHz Is ±125 ps - Jitter (cyc - cyc) at 60 MHz to 175 MHz Is
Typ = 65 ps - Advanced Deep Submicron Process Results in More Than 40% Lower Power
Consumption Versus Current Generation PC133 Devices - Auto Frequency Detection to Disable Device (Power-Down Mode)
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
- Separate Output Enable for Each Output Bank
- External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
- 25- On-Chip Series Damping Resistors
- No External RC Network Required
- Operates at 3.3 V
- APPLICATIONS
- DRAM Applications
- PLL Based Clock Distributors
- Non-PLL Clock Buffer
Specifications
The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.
Product Status | Obsolete | Programmable | Not Verified |
Type | PLL Clock Driver | PLL | Yes with Bypass |
Input | LVTTL | Output | LVTTL |
Ratio - Input:Output | 2:10 | Differential - Input:Output | No/No |
Frequency - Max | 175MHz | Divider/Multiplier | No/No |
Voltage - Supply | 3V ~ 3.6V | Operating Temperature | 0°C ~ 85°C |
Mounting Type | Surface Mount | Package / Case | TSSOP-24 |
Supplier Device Package | 24-TSSOP | Base Product Number | CDCVF2509 |
Manufacturer | Texas Instruments | Product Category | Clock Drivers & Distribution |
RoHS | Details | Series | CDCVF2509A |
Minimum Operating Temperature | 0 C | Maximum Operating Temperature | + 85 C |
Mounting Style | SMD/SMT | Brand | Texas Instruments |
Product | Clock Drivers | Product Type | Clock Drivers & Distribution |
Factory Pack Quantity | 2000 | Subcategory | Clock & Timer ICs |
Unit Weight | 0.003157 oz |
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