CDCU877RHAR

Name: CDCU877RHAR
Rating: 4.5 (10 reviews)

Zero Delay Buffer 10-Out Differential 40-Pin VQFN EP T/R

8,870 Effective Inventory

CDCU877RHAR

Effective Inventory8,870

Zero Delay Buffer 10-Out Differential 40-Pin VQFN EP T/R

Manufacturer Part # : CDCU877RHAR
Package/Case: VQFN-40
Part Status : ACTIVE
Brand: Texas Instruments
Product Categories : Clock buffers
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CDCU877RHAR DataSheet

Pricing (USD)

Quantity	Unit Price	Ext. Price
1	$25.168	$25.17
200	$9.741	$1,948.20
500	$9.398	$4,699.00
1000	$9.230	$9,230.00

These prices are subiect to market fluctuations and quote submission is required.

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Details

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock inputpair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV_DD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C.

Key Features

1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle): ±30 ps
Low Output Skew: 35 ps
Low Period Jitter: ±20 ps
Low Dynamic Phase Offset: ±15 ps
Low Static Phase Offset: ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
52-Ball µBGA (MicroStar™ Junior BGA, 0,65-mm pitch) and 40-Pin MLF
External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks
Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300
Fail-Safe Inputs

MicroStar is a trademark of Texas Instruments.

Specifications

The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.

Function	Memory interface	Additive RMS jitter (typ) (fs)	30
Output frequency (max) (MHz)	340	Number of outputs	10
Output supply voltage (V)	1.8	Core supply voltage (V)	1.8
Output skew (ps)	35	Features	DDR2 PLL
Operating temperature range (°C)	-40 to 85	Rating	Catalog
Output type	LVCMOS